The present invention generally relates to computer memory systems using Dynamic Random Access Memory (DRAM) components, where data is stored in the memory components as individual bits of data which may have only one of two states, a logical one or a logical zero. These bits of data are typically moved in and out of the DRAM Components in groups. The groups of data are then handled by the memory system as a unit. The DRAM components are susceptible to two types of errors--hard errors and soft errors. A hard error is a permanent error and represents a memory location being stuck-at-1 or stuck-at-0. A soft error is temporary, random, and correctable since it is non-recurring and non-destructive. In typical DRAM memory systems some type of scheme for handling corrupted data from the memory component is used. The scheme may be a method of only detecting errors or it may be a method of detecting and correcting errors.
Typical memory systems which provide for error detection and correction do so using check bits which are generated from the group of data bits using a Hamming code. When the group of data is written to the DRAM Component both the data and its associated check bits are stored in the memory component. When a group of data is read from the DRAM component both the data and its associated check bits are retrieved from the DRAM component. The data and check bits are used to generate syndrome bits which not only indicate whether or not the data group has been corrupted but also provide enough information to correct the invalid data.
Typical memory systems which only check for corrupted data from the DRAM component do so using a parity check algorithm. The parity algorithm requires that a bit of data, referred to as a parity bit, be generated which indicates the number of logical ones within a particular group of data bits being stored in the DRAM component. When the group of data is written to the DRAM component both the data and its associated parity bit are stored in the memory component. When a group of data is read from the DRAM component both the data and its associated parity bit are retrieved from the DRAM component. A second parity bit is generated, based on the group of data bits read from memory, and compared to the first parity bit. If the two parity bits match then no error is said to have occurred. If the two parity bits do not match then an error is said to have occurred.
Both schemes of handling corrupt data have advantages in different applications. The parity algorithm is an efficient method of error checking because only one parity bit is required per data group. However, the parity algorithm does not provide enough information to determine which data bit or bits are wrong. Hamming code schemes are most efficient when the number of data bits in the group for which the check bits have been generated is large. For example, a group of 8 data bits requires 5 check bits which is a 63% overhead while a group of 32 data bits required only 7 check bits which is a 13% overhead.
The problem with the Hamming code scheme is that in order to write a partial data group to memory and still maintain valid check bits for the whole data group, the complete data group must first be read from memory, combined with the partial data group, new check bits generated and the complete updated data group with its associated check bits written to the memory. This read-modify-write operation must occur every time a partial data group write is performed thus degrading the performance of the memory system.